1. Field of the Invention
This invention relates generally to an improved resistive dividing or scaling network which may be trimmed to achieve either higher or lower scaling factors and more specifically, to a resistive dividing network useful in scaling the relative combinations of the higher and lower order bits in a digital to analog converter (DAC hereinafter).
2. Description of the Prior Art
In the past, integrated circuit DAC's have been configured with the higher order bits binarily divided in a main ladder and the lower order bits binarily divided in an output R-2R ladder. The bits are summed at an output node, such as shown in FIG. 1, where I.sub.1, I.sub.2 and I.sub.3 represent the higher order bit currents and I.sub.4 -I.sub.7 (and higher-not shown) represent equal current sources which are binarily divided in the R-2R ladder sequence shown in FIG. 1. The current sources I.sub.1 -I.sub.7 . . . are understood to be toggled by digitally-controlled bit switches (not shown).
Initially, the circuit is adjusted by a trim to set the I.sub.1,/I.sub.2,/I.sub.3 ratio as well as by an independent trim so that current sources I.sub.4-I.sub.7 . . . make binary contributions at the output. Such a procedure may often result in an incorrect ratio between the higher order bits I.sub.1 -I.sub.3 and the lower order bits I.sub.4 -I.sub.7 . . .
The lower order bit outputs usually are divided or scaled before summation with the higher order bits. A trimmable scaling or dividing network can be used to divide the entire output of the R-2R ladder without changing the binary division accomplished within the output ladder. The utility of this technique is severely limited if the trimming method (which conventionally adjusts resistor values upward) can only increase or only decrease the relative contribution of the lower order bits with respect to the higher order bits.
In the past, it was possible to build a DAC without using a R-2R ladder network by incorporating a quad current switch approach. In a quad current switch, four current sources and switches would be grouped together, with their currents scaled at a ratio of 8:4:2:1. In a 16-bit DAC, for example, there would be four quad current switches. The output of the first quad current switch would be coupled directly to the DAC output. The second quad current switch output would be divided by 16, the third quad current switch output would be divided by 256, and the fourth quad current switch would be divided by 4096. The dividing network used to scale the respective quad current switches was comprised of a pair of resistors and was usually trimmable both up and down. For example, between the first and second quad current switches, the dividing circuit would be comprised of a first trimmable resistor of value R and second trimmable resistor of value 15R, so as to achieve the 16:1 ratio between the first and second quad current switches. Between the second and third quad current switches, the dividing circuit was comprised of trimmable resistors having respective values R and 255R. Between the third and fourth quad current switches, the dividing circuit networks was comprised of trimmable resistors having a ratio of R to 4095R.
The trimmable resistors in the dividing circuits were difficult to build in the ratios of 1:15, 1:255 and 1:4095, and would change with age. In addition it was very difficult to trim the resistors (up and down) to get accurate sensitivity and resolution. As a result, the quad current switch approach has been supplanted by the R-2R ladder network. However a need existed to provide, for modern DACs incorporating R-2R ladder networks, a trimmable scaling or dividing network which both maintains the desired circuit impedance levels, allows independent trimming of the bit ratios, and can be trimmed to effect a relative increase or decrease of the lower order bit contribution at the output.